1. Field of the Invention: o The present invention relates to an anti .alpha.-particle structure for a semiconductor device, for example, a low temperature operation MOS memory. More particularly, the present invention pertains to a low temperature operation memory structure having a reduced collection efficiency at which undesirable electrons (or holes) excited by .alpha.-particles are collected in memory nodes.
2. Description of the Prior Art:
Occurrence of soft errors which are caused by .alpha.-particles is one of the critical problems concerning the reliability of semiconductor memories. More specifically, a-particles emitted by radioactive elements (U-238, Th-230, etc.) in memory element packaging materials generate noise charges in the element which may destroy the storage information, resulting in a mal-operation.
A typical conventional anti .alpha.-particle device structure for memory elements is disclosed in Japanese Patent Laid-Open Nos. 59-84461 (1984), 59-94451 (1984) and a literature entitled "A P-Type Buried Layer for Protection Against Soft Errors in High Density CMOS Static RAMs", H. Momose et al., IEEE IEDM, Technical Digest, pp. 706-709, 1984. In this prior art, a p.sup.+ layer is formed under a memory node (n.sup.+ impurity layer) to thereby prevent noise charges from flowing into the memory node. A conventional device structure for MOS static memory is shown in FIG. 2. In the figure, the reference numeral 21 denotes an n-type Si substrate, 22 a p-type well, 23 an n.sup.+ impurity layer which defines a memory node in which the information charge of a memory cell is accumulated, 24 a gate electrode (transfer MOS electrode which is connected to a word line) of a MOS transistor, 25 an n.sup.+ impurity layer which is connected to a data line, and 26 a p.sup.+ impurity layer which is formed under the memory node. When .alpha.-particles are applied to the memory cell from the upper side thereof, electrons 27 and holes 28 are generated along the track 29. When the memory node is at a high voltage level, the generated electrons flow into the n.sup.+ impurity layer which defines the memory node 23 and lowers the voltage level of the node, thus causing a mal-operation (soft error). According to the illustrated device structure, it is possible to effectively prevent the above-described noise electrons 27 from flowing into the memory node 23 by means of the potential barrier which is formed at the boundary between the p.sup.+ -layer 26 and the p-layer 22. Assuming that the impurity concentration difference between the p.sup.+ -layer 26 and p-layer 22 is 10.sup.2 cm.sup.-3 or more, a potential barrier of 0.1 eV or more is present at the boundary between the layers under room temperature conditions, and it is therefore possible to effectively prevent the noise electrons 27 from flowing into the memory node 23.